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| SSRAM Austin Semiconductor, Inc. 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through FEATURES * Fast access times: 8, 10, and 15ns * Fast clock speed: 113, 100, and 66 MHz * Fast clock and OE\ access times * Single +3.3V +0.3V/-0.165V power supply (VDD) * SNOOZE MODE for reduced-power standby * Common data inputs and data outputs * Individual BYTE WRTIE control and GLOBAL WRITE * Three chip enables for simple depth expansion and address pipelining * Clock-controlled and registered addresses, data I/Os and control signals * Interally self-timed WRITE cycle * Burst control pin (interleaved or linear burst) * Automatic power-down * Low capacitive bus loading * Operating Temperature Ranges: - Military -55oC to +125oC - Industrial -40oC to +85oC NC NC NC V DD Q VSS NC NC DQb DQb VSS V DD Q DQb DQb VSS V DD NC VSS DQb DQb V DD Q VSS DQb DQb DQPb NC VSS V DD Q NC NC NC AS5SS256K18 PIN ASSIGNMENT (Top View) 100-pin TQFP SA SA CE\ CE2 NC NC bwB\ BWa\ CE2\ V DD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ SA SA OPTIONS * Timing 7.5ns/8ns/113 MHz 8.5ns/10ns/100 MHz 10ns/15ns/66 MHz * Packages 100-pin TQFP * Operating Temperature Ranges: - Military -55oC to +125oC - Industrial -45oC to +85oC *available as IT only. MARKING -8* -9 -10 DQ IT XT No. 1001 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 1 1 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SA NC NC V DD Q VSS NC DQPa DQa DQa VSS V DD Q DQa DQa VSS NC V DD ZZ DQa DQa V DD Q VSS DQa DQa NC NC VSS V DD Q NC NC NC **pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities. For more products and information please visit our web site at www.austinsemiconductor.com GENERAL DESCRIPTION The Austin Semiconductor, Inc. Synchronous Burst SRAM family employs high-speed, low power CMOS designs that are fabricated using an advanced CMOS process. ASI's 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\), two additional chip enables for easy depth expansion (CE2\, AS5SS256K18 Rev. 2.0 12/00 CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and global write (GW\). Asynchronous inputs include the output enable (OE\), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE\, is also asynchronous. WRITE cycles can be from one to two bytes wide, as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP\) or address status controller (ADSC\) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV\). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on this x18 device BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins and DQPb. GW\ LOW causes all bytes to be written. Parity bits are available on this device. ASI's 4Mb Synchronous Burst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium(R), and PowerPC systems and those systems that benefit from a wide synchronous data bus. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 MODE SA SA SA SA SA1 SA0 DNU DNU VSS V DD NF** NF** SA SA SA SA SA SA SA SSRAM Austin Semiconductor, Inc. PIN DESCRIPTIONS PIN NUMBERS 37, 36, 32-35, 44-50, 80-82, 99, 100 93, 94 AS5SS256K18 SYM SA0, SA1, SA BWa\ BWb\ TYPE Input Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enables is LOW for a WRITE cycle and HIGH for a READ cycle. BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins and DQPb. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the BWE\ and BWx\ lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and Conditions the internal use of ADSP\. CE\ is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during WRITE cycle, ADV\ must be HIGH at the rising edge of the first clock after an ADSP\ cycle is initiated. Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC\, but dependent upon CE\, CE2, and CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered if CE2 if LOW or CE2\ is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE\ is LOW. ADSC\ is also used to place the chip into powerdown state when CE\ is HIGH. Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Do not alter input state while device is operating. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a lowpower standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins. Input data must meet setup and hold times around the rising edge of CLK. 87 88 BWE\ GW\ Input Input 89 CLK Input 98 CE\ Input 92 97 86 83 CE2\ CE2 OE\ ADV\ Input Input Input Input 84 ADSP\ Input 85 ADSC\ Input 31 MODE Input 64 ZZ Input (a) 58, 59, 62, 63, 68, 69, 72, 73 (b) 8, 9, 12,13, 18, 19, 22, 23 74, 24 15, 41,65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 67 71, 76, 90 38, 39 1-3, 6, 7, 16,25, 28-30, 51-53, 56,57, 66, 75, 78, 79, 95, 96 42, 43 DQa DQb Input/ Output NC/DQPa NC/DQPb VDD VDDQ VSS NC/ I/O Supply Supply Supply No Connect/Parity Data I/Os: Byte "a" is DQPa pins; Byte "b" is DQPb pins. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characterics and Operating Conditions for range. Ground: GND DNU NC ------- Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. No Function: These pins are internally connected to the die and will have the capacitance of input pins. It is allowable to leave these pins unconnected or driven by signals. NF AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SSRAM Austin Semiconductor, Inc. AS5SS256K18 INTERLEAVED BURST ADDRESS TABLE (MODE=NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE=LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS FUNCTION READ READ WRITE Byte "a" WRITE Byte "b" WRITE All Bytes WRITE All Bytes GW\ H H H H H L BWE\ H L L L L X BWa\ X H L H L X BWb\ X H H L L X NOTE: Using BWE\ and BWa\ through BWb\, any one or more bytes may be written. FUNCTIONAL BLOCK DIAGRAM 18 SA0, SA1, SA MODE ADV\ CLK ADDRESS REGISTER 18 2 BINARY COUNTER AND LOGIC Q0 CLR Q1 SA0-SA1 SA1' 16 18 SA0' ADSC\ ADSP\ BYTE "b" WRITE DRIVER BWb\ BYTE "b" WRITE REGISTER 9 9 9 BWa\ BWE\ GW\ CE\ CE2 CE2\ OE\ BYTE "a" WRITE REGISTER BYTE "a" WRITE DRIVER 9 256K x 9 x 2 MEMORY ARRAY 18 SENSE AMPS 18 OUTPUT BUFFERS 18 DQs DQPa DQPb 18 ENABLE REGISTER 2 INPUT REGISTERS NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SSRAM Austin Semiconductor, Inc. TRUTH TABLE OPERATION DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst ADDRESS USED NONE NONE NONE NONE NONE NONE EXTERNAL EXTERNAL EXTERNAL EXTERNAL EXTERNAL NEXT NEXT NEXT NEXT NEXT NEXT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CE\ CE2\ CE2 ZZ ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK H L L L L X L L L L L X X H H X H X X H H X H X X H X H X L L L L L X X X X X X X X X X X X X L X L X X H H H H H X X X X X X X X X X X X L L L L L H L L L L L L L L L L L L L L L L L X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D AS5SS256K18 NOTES: 1. X means "Don't Care." \ means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\) and BWE\ are LOW or GW\ is LOW. WRITE\ = H for a ll BWx\, BWE\, GW\ HIGH. 3. BWa\ enables WRITEs to DQas and DQPa. BWb\ enables WRITEs to DQbs and DQPb. 4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SSRAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS............-0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS.........-0.5V to +4.6V Storage Temperature (plastic) .....................-55C to +125C Max Junction Temperature**.......................................+150C Short Circuit Output Current........................................100mA AS5SS256K18 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC and -40oC (0V DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS TA = 25C; f = 1MHz; VDD = 3.3V SYM CI CO CA CCK MAX 4 5 3.5 3.5 UNITS pF pF pF pF NOTES 6 6 6 6 THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 SYM JA JC TYP 46 2.8 UNITS C/W C/W NOTES 6 6 NOTES: 1. All voltages referenced to VSS (GND) 2. Overshoot: VIH < +4.6V for t < tKC/2 for I < 20mA Undershoot: VIL > -0.7V for t < tKC/2 for I < 20mA Power-up: VIH < +3.6V and VDD<3.135V for t < 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher then the stated DC values. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only. 6. This parameter is sampled. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SSRAM Austin Semiconductor, Inc. AS5SS256K18 IDD ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC and -40oC PARAMETER Power Supply Current: Operating CONDITIONS Device selected; all inputs < VIL or > VIH; Cycle time > tKC (MIN); VDD = MAX; Outputs Open Device selected; VDD = MAX; ADSC\, ADSP\, SYM IDD -8 375 -10 250 UNITS NOTES mA 2, 3, 4 Power Supply Current: Idle ADV\, GW\, BWx\ > VIH; All inputs < VSS +0.2 or > VDDQ -0.2; Cycle time > KC (MIN); Outputs Open Device deselected; VDD = MAX; t IDD1 100 85 65 mA 2, 3, 4 CMOS Standby All inputs < Vss +0.2 or > VDDQ -0.2; All inputs static; CLK frequency =0 Device deselected; VDD = MAX; All inputs < VIL or > VIH; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ISB2 10 10 10 mA 3, 4 TTL Standby ISB3 25 25 25 mA 3, 4 Clock Running ASDP\, ADV\, GW\, BWx\ > VIH; All inputs < VSS +0.2 or > VDDQ -0.2; Cycle time > KC (MIN) t ISB4 100 85 65 mA 3, 4 NOTES: 1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration. 2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 3. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode). 4. Typical values are measured at 3.3V, 25C and 15ns cycle time. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SSRAM Austin Semiconductor, Inc. AS5SS256K18 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) -55oC < TA < +125oC and -40oC Clock cycle time Clock frequency Clock HIGH time Clock LOW time SYMBOL tKC tKF tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tAS tADSS tAAS tWS tDS tCES tAH tADSH tAAH tWH tDH tCEH -8 MIN 8.8 113 2.5 2.5 7.5 3.0 3.0 -9 MAX MIN 10 100 4.0 4.0 8.5 -10 MAX MIN 15 66 MAX UNITS ns MHz ns ns NOTES 2 2 OUTPUT TIMES Clock to output valid 10 ns ns ns Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE\ to output valid OE\ to output in Low-Z OE\ to output in High-Z SETUP TIMES Address Address status (ADSC\, ADSP\) Address advance (ADV\) Byte write enables (BWa\-BWb\, GW\, BWE\) Data-in Chip enable (CE\) HOLD TIMES Address Address status (ADSC\, ADSP\) Address advance (ADV\) Byte write enables (BWa\-BWb\, GW\, BWE\) Data-in Chip enable (CE\) 1.5 1.5 4.2 4.2 0 4.2 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 3.0 3.0 5.0 5.0 0 5.0 1.8 1.8 1.8 1.8 1.8 1.8 0.5 0.5 0.5 0.5 0.5 0.5 3.0 3.0 5.0 5.0 0 5.0 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 3 3, 4, 5 3, 4, 5 6 3, 4, 5 3, 4, 5 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) unless otherwise noted. 2. Measured as HIGH above VIH and LOW below VIL. 3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O. 4. This parameter is sampled. 5. Transition is measured 500mV from steady state voltage. 6. OE\ is a "Don't Care" when a byte write enable is sampled LOW. 7. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is defined by at least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times. 8. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to remain enabled. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SSRAM Austin Semiconductor, Inc. AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load VIH = (VDD/2.2) + 1.5V VIL = (VDD/2.2) - 1.5V 1ns VDD/2.2 VDDQ/2.2 See Figures 1 and 2 AS5SS256K18 OUTPUT LOADS DQ Z 0=50 50 LOAD DERATING CURVES ASI's 256K x 18 Synchronous Burst SRAM timing is dependent upon the capacitive loading on the outputs. Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF SNOOZE MODE SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not quaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. Fig. 2 OUTPUT LOAD EQUIVALENT SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current NOTE: 1. This parameter is sampled. CONDITIONS ZZ > VIH SYM ISB2Z tZZ tRZZ tZZI tRZZI MIN MAX 10 tKC UNITS mA ns ns NOTES 1 1 1 1 tKC tKC 0 ns ns SNOOZE MODE WAVEFORM CLK t ZZ ZZ ISUPPLY ALL INPUTS* * Except ZZ AS5SS256K18 Rev. 2.0 12/00 t RZZ t ZZI ISB2 t RZZI 4321 4321 4321 4321 5439 2 0 541 3 54021765432121 01 8 321765432121 218 9 541 3 54321765432121 218 9 543 54321765432121 218 09 543 8 Don't Care Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 21 21 21 21 321 321 321 321 21 21 21 21 21 21 21 21 21 21 21 21 4321 4321 4321 4321 321 321 321 321 4321 4321 4321 4321 6 4329 1 9 65210187654321 54321 65210987654321 432 65210187654321 4321 210987654321 1 65210987654321 4321 65210987654321 4321 65210987654321 4321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543109876543210987654321 6542109876543210987654321 2321 1 221 6543109876543210987654321 2221 1 2 6543109876543210987654321 2321 1 6543109876543210987654321 2121 1 2 6543109876543210987654321 2221 6542109876543210987654321 2121 765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432109876543212109876543210987654321098765432121098765432109876543210987654321 54321 54321 5 54321 1 54329876543254321 9 1 14321 54329876543254321 9 187654321 1 54321876543254321 54329876543254321 1 9 54321 54321876543254321 1 54321 1 321098765432121 1 7 5 321098765432121 16543 74321 321098765432121 1 76543 1 321098765432121 76543 321098765432121 16543 76543 321098767654321 1 76543 321098765432121 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654221 2121 1 6542109876543210987654321 23109876543210987654321 6543109876543210987654321 2321 1 2 6543109876543210987654321 2321 1 2 6543109876543210987654321 2221 1 6542109876543210987654321 2121 987654321098765432121098765432109876543210987654321210987654321098765432109876587654321 2 987654321098765432121098765432109876543210987654321210987654321098765432109876543254321 87611 43211 1 2 987654321098765432121098765432109876543210987654321210987654321098765432109876587614321 43251 2 2 987654321098765432121098765432109876543210987654321210987654321098765432109876587654321 43211 987654321098765432121098765432109876543210987654321210987654321098765432109876587654321 43221 2 987654321098765432121098765432109876543210987654321210987654321098765432109876587654321 43211 87687654321 54321 87687654321 54321 32 321 87687654321 54321 321 87687654321 54321 87687654321 54321 1 87687654321 54321 876543214321 21 8765 876543214321 21 87 43 876543214321 2165 8721 876543214321 21 8765 876587654321 21 8765 876543214321 2165 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 654321 654321 654321 654321 654321 654321 654321 5 4321 54321 43211 4321 1 5432987654324321 44329 3211 1 5432187654324321 4321987654324321 1 5432187654324321 43211 4321 1 5432187654324321 43219 1 5432987654324321 43219 1 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 7654321 7654321 7654321 7654321 7654321 7654321 54321 54321 54321 54321 54321 54321 NOTE: AS5SS256K18 Rev. 2.0 12/00 BWE\, GW\, BWa\-BWb\ ADDRESS CE\ (Note 2) ADSC\ ADSP\ ADV\ CLK OE\ 1. 2. 3. 4. Q Q(A2) referes to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW. Timing is shown assuming that the device was not enabled before entering into this sequence. Outputs are disabled tKQHZ after deselect. High-Z tADSS READ TIMING PARAMETERS tKQLZ -8 -9 -10 SYM MIN MAX MIN MAX MIN MAX UNITS 8.8 10 15 ns tKC tOEHZ tOELZ tOEQ tKQHZ tKQLZ tKQX tKQ tKL tKH tKF Austin Semiconductor, Inc. t CES tCEH t WS t WH t AS A1 tAH tADSH tKQ 1.5 1.5 2.5 2.5 SINGLE READ 0 tOEQ 113 4.2 4.2 4.2 7.5 Q(A1) tADSS tKH tOEHZ 3.0 3.0 3.0 3.0 t KC tKL 0 100 5.0 5.0 5.0 8.5 A2 tADSH 3.0 3.0 4.0 4.0 0 tOELZ tKQ tKQX t AAS tAAH READ TIMING Q(A2) 5.0 5.0 5.0 10 66 MHz ns ns ns ns ns ns ns ns ns (NOTE 1) Q(A2+1) 9 tCEH tADSS tADSH tAH tWS tAAS -8 -9 -10 SYM MIN MAX MIN MAX MIN MAX UNITS 1.5 1.8 2.0 ns tAS tWH tAAH tCES Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 0.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 1.5 Q(A2+2) ADV\ suspends burst. BURST READ 0.5 0.5 0.5 0.5 0.5 1.8 1.8 1.8 1.8 Q(A2+3) 0.5 0.5 0.5 0.5 0.5 2.0 2.0 2.0 2.0 AS5SS256K18 Q(A2) Burst wraps around to its initial state. ns ns ns ns ns ns ns ns ns SSRAM Q(A2+1) Deselect Cycle (Note 4) Q(A2+2) tKQHZ 54321 1 5432 54321 54321 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 321 321 321 21 21 21 321 321 321 54321324321 654 21 321 11 21 2 1 54354324321 21 2 61 54654324321 221 11 2109876543212109876543210987654321098765432121098765432109876543210985654321 7432121 4321 6543 2109876543212109876543210987654321098765432121098765432109876543210987987654321 5654321 2109876543212109876543210987654321098765432121098765432109876543210987987654321 7987654321 5654321 4321 2109876543212109876543210987654321098765432121098765432109876543210987987654321 5654321 4321 2109876543212109876543210987654321098765432121098765432109876543210985987654321 5654321 4321 2109876543212109876543210987654321098765432121098765432109876543210987987654321 4321 987654321 987654321 987654321 987654321 987654321 987654321 4329876543254321 1 14321 4321 4321 1 9 9 4329876543254321 4321876543254321 1 1 14321 4321876543254321 1 4321876543254321 9 1 4329876543254321 1 7654321 7654321 7654321 7654321 7654321 7654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54311 4320987654354321 24321 1 1 5431 4322 2 0 21 0 24321 54301 4321987654354321 2 11 54321 4320987654354321 21 21 54311 4322987654354321 21 5431987654354321 4320987654354321 21 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 5432109876543210987657654321 4321 21 5432109876543210987657654321 4321 5432109876543210987657654321 4321 5432109876543210987657654321 4321 21 21 5432109876543210987657654321 4321 5432109876543210987657654321 4321 5432109876543210987657654321 4321 543209876543210987654321210987654321098765432109876543254321 1 1 1 54320 1 54321 09876543210987654321210987654321098765432109876543254321 1 543209876543210987654321210987654321098765432109876543254321 1 54321 54320 1 1 54321 1 54321 1 54321 543219876543210987654321210987654321098765432109876543254321 1 543209876543210987654321210987654321098765432109876543254321 1 543219876543210987654321210987654321098765432109876543254321 543209876543210987654321210987654321098765432109876543254321 1 5432 4321 1 4321 5430987654324321 2 01 1 4321 5321987654324321 2 01 1 4321987654324321 54301 44311 2 01 4321 1 54321 2 4321 4320987654324321 1 5431987654324321 1 4322987654324321 5430987654324321 1 1 210987654321 26543 1 6 4 21098765432121 21543 5632121 1 21098765432121 26543 21098765432121 26543 1 21098765432121 21543 1 21098762654321 21543 6 21098765432121 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 5432 4321 24321 1 54311 4320987654354321 2 0 11 24321 1 54321 4320987654354321 2 01 21 54311 4322987654354321 21 5430987654354321 4320987654354321 21 54311 4321987654354321 2 21 54321 54321 54321 1 54329876543254321 9 1876543254321 1 1 54321876543254321 9 1 54329876543254321 9 1 54329876543254321 1 54321 54321876543254321 1 54321 1 4321 4321 4321 4321 4321 4321 987654321 987654321 987654321 987654321 987654321 987654321 54321 54321 54321 54321 1 54321 54329876543254321 1 1 9 54321876543254321 9 1876543254321 1 54321876543254321 1 9 54321876543254321 9 1 54329876543254321 1 54321 54321 4321 4321 1 54321 5432987654324321 1 1 9 5432187654324321 9 187654324321 1 5432187654324321 1 9 5432187654324321 9 1 5432987654324321 1 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 4321 4321 4321 4321 4321 4321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 1098765432109876587654321 4321 1098765432109876587654321 4321 1098765432109876587654321 4321 2 21 1098765432109876587654321 4321 1 1098765432109876587654321 4321 1098765432109876587654321 4321 876543321098765432121098765432109876543210987687621321 1 4 54354 21 876543321098765432121098765432109876543210987687654321 121 421 54324 876543321098765432121098765432109876543210987687654321 321 1 4 87621 54321 21 876543321098765432121098765432109876543210987687654321 1 421 54351 876543321098765432121098765432109876543210987654321321 1 421 54321 876544321098765432121098765432109876543210987687654321 121 876587654321 4321 876587654321 4321 876587654321 4321 321 876587654321 4321 321 876587654321 4321 876587654321 4321 876543 27 1 876543214321 27214321 165 87654321432 2165 4765 1 7 3 876543214321 2165 876521214321 2765 1 876543214321 765 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 4321 4321 4321 4321 4321 4321 ADSP\ CLK tADSS Austin Semiconductor, Inc. tADSH 654321 654321 654321 654321 654321 654321 654321 654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 5431 2 21 1 5430987654354321 43221 0 21 54321 4320987654354321 2 01 11 24321 5321987654354321 4321987654354321 21 1 54321 44301 2 0 21 5431987654324321 4321987654354321 24321 4320987654354321 1 54321 54321 1 54329876543254321 1 1 9 54321876543254321 9 1876543254321 1 54321876543254321 9 1 54321 54329 1 54321 1 9 54321876543254321 54321876543254321 1 54329876543254321 1 4321 4321 4321 4321 4321 4321 4321 AS5SS256K18 Rev. 2.0 12/00 NOTE: BEW\, BWa\ - BWb\ ADDRESS CE\ (NOTE 2) ADSC\ ADV\ GW\ OE\ Q D 1. D(A2) refers to output from address A2. D(A2+1) refres to output from the next internal burst address following A2. 2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW. 3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV\ must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BWE\, BWa\ and BWb\ LOW. BURST READ High-Z tCES t CEH tAS A1 t AH WRITE TIMING PARAMETERS -8 -9 -10 SYM MIN MAX MIN MAX MIN MAX UNITS 8.8 10 15 ns tKC tWS tAAS tADSS tAS tOEHZ tKL tKH tKF SINGLE WRITE (Note 3) tDS t DH D(A1) 1.5 1.5 1.5 1.5 2.5 2.5 t OEHZ tKH 113 4.2 BYTE WRITE signals are ignored when ADSP\ is LOW. t KC tKL 1.8 1.8 1.8 1.8 3.0 3.0 A2 (Note 4) 100 5.0 2.0 2.0 2.0 2.0 4.0 4.0 D(A2) WRITE TIMING (Note 5) 5.0 66 (Note 1) MHz D(A2+1) ns ns ns ns ns ns ns tWS t WH 10 tCES tCEH tDH tWH tAAH tADSH tAH -8 -9 -10 SYM MIN MAX MIN MAX MIN MAX UNITS 1.5 1.8 2.0 ns tDS ADSC\ extends burst. t ADSS D(A2+1) BURST WRITE 0.5 0.5 0.5 0.5 0.5 0.5 1.5 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ADV\ suspends burst. D(A2+2) 0.5 0.5 0.5 0.5 0.5 0.5 1.8 D(A2+3) 0.5 0.5 0.5 0.5 0.5 0.5 2.0 ns ns ns ns ns ns ns D(A3) A3 AS5SS256K18 tADSH tAAS t AAH tWS tWH Extended BURST WRITE D(A3+1) SSRAM Don't Care D(A3+2) 5432 54321 54321 54321 1 54321 654321 1 654321 6 654321 654321 5432 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 65421098765432121098765432109876543210987654321 2221 1 65431098765432121098765432109876543210987654321 2321 1 2 65431098765432121098765432109876543210987654321 2321 1 65431098765432121098765432109876543210987654321 2121 1 2 65431098765432121098765432109876543210987654321 2221 65421098765432121098765432109876543210987654321 2121 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 54321 4321 14321 4328 43287654321210987654321098765432109876543254321 1 1 14321 43287654321210987654321098765432109876543254321 1 87654321210987654321098765432109876543254321 1 43287654321210987654321098765432109876543254321 1 1 43217654321210987654321098765432109876543254321 1 1 43287654321210987654321098765432109876543254321 1 4321 43287654321210987654321098765432109876543254321 1 1 4321 1 4321 4329876543214321 1 9 1 4321876543254321 9 1876543254321 1 4321876543254321 9 4329876543254321 9 1 4329876543254321 1 4321 4321876543254321 1 14321 54321 54321 54321 54321 1 54321 54329876543254321 1 9 1 54321876543254321 9 1876543254321 1 1 54321876543254321 9 54329876543254321 9 1 54329876543254321 1 54321 54321876543254321 1 1 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 543210987654321 543210987654321 543210987654321 543210987654321 543210987654321 543210987654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54329876543254321 1 54321 54321 1 9 54321 54321 1 54329876543254321 54321876543254321 1 1 1 9 54321876543254321 1 54321876543254321 1 9 54329876543254321 987654321 1 321 321 321 321 321 321 5432 876541 8765 8765432121098765432109876543210987687654321 32121098765432109876543210987654324321 1 54321 87651 8765432121098765432109876543210987687654321 1 3 54321 1 8765432121098765432109876543210987654324321 1 21 1 321 8765432121098765432109876543210987687654321 1 21 8765432121098765432109876543210987687654321 121 54321 32 876587654321 4321 876587654321 4321 876587654321 4321 321 1 876587654321 4321 876587654321 4321 876587654321 4321 87687654321 54321 87687654321 54321 87687654321 54321 321 87687654321 54321 321 87687654321 54321 87687654321 54321 321 321 321 321 321 321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 ADSP\ CLK t ADSS Austin Semiconductor, Inc. tADSH 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 BWE\, GW\ BWa\ - BWb\ ADDRESS CE\ (Note 2) ADSC\ ADV\ OE\ D A1 High-Z t CES t AS A2 tCEH tAH tKH tOEHZ t KC tKL A3 READ/WRITE TIMING6 t DS tDH t WS D(A3) t WH A4 tOELZ tKQ (NOTE 1) 21 21 21 21 21 21 21 21 21 1 1 1 1 321 321 321 321 4321 4321 4321 4321 NOTE: AS5SS256K18 Rev. 2.0 12/00 Q 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4. 2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP\, ADSC\, or ADV\ cycle is performed. 4. GW\ is HIGH. 5. Back-to-back READs may be controlled by either ADSP\ or ADSC\. 6. Timing is shown assuming that the device was not enabled before entering into this sequence. READ/WRITE PARAMETERS tADSS tAS tOEHZ tOELZ tKQ tKL tKH tKF -8 -9 -10 SYM MIN MAX MIN MAX MIN MAX UNITS 8.8 10 15 ns tKC Back-to-Back READS (NOTE 5) Q(A1) 1.5 1.5 2.5 2.5 0 113 3.5 7.5 Q(A2) 1.8 1.8 3.0 3.0 0 100 4.2 8.5 2.0 2.0 4.0 4.0 SINGLE WRITE 0 5.0 10 66 MHz ns ns ns ns ns ns ns 11 tDH tADSH tWH tDS tCEH tAH tCES -8 -9 -10 SYM MIN MAX MIN MAX MIN MAX UNITS 1.5 1.8 2.0 ns tWS Q(A4) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 0.5 0.5 0.5 0.5 0.5 1.5 1.5 Q(A4+1) BURST READ 0.5 0.5 0.5 0.5 0.5 1.8 1.8 Q(A4+2) Don't Care 0.5 0.5 0.5 0.5 0.5 2.0 2.0 Q(A4+3) AS5SS256K18 Back-to-Back WRITEs D(A5) A5 SSRAM ns ns ns ns ns ns ns Undefined D(A6) A6 SSRAM Austin Semiconductor, Inc. AS5SS256K18 MECHANICAL DEFINITIONS ASI Case #1001 (Package Designator DQ) 16.00 +0.20/-0.05 14.00 + 0.10 Pin #1 ID 22.10 + 0.10/-0.15 DETAIL A 0.25 Gage Plane 0.10 +0.10/-0.05 20.10 + 0.10 1.00 TYP 0.62 1.40 + 0.05 0.10 1.50 + 0.10 NOTE: 0.65 See Detail A 0.15 +0.03/-0.02 0.32 +0.06/-0.10 0.60 + 0.15 1. All dimensions in Millimeters (MAX/MIN) or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protursion is 0.25mm per side. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS5SS256K18 Rev. 2.0 12/00 12 SSRAM Austin Semiconductor, Inc. AS5SS256K18 ORDERING INFORMATION EXAMPLE: AS5SS256K18DQ-8/IT Device Number AS5SS256K18 AS5SS256K18 AS5SS256K18 Package Speed ns Process Type DQ -8 IT only DQ -9 /* DQ -10 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range -40oC to +85oC -55oC to +125oC AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 |
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